Why Journal ICON

A Bi-Monthly and Multidisciplinary Journal, High Quality Papers, Peer Review process, Open access policy, Fast Publication, Full Archive for life time

Why Journal ICON

A Bi-Monthly and Multidisciplinary Journal, High Quality Papers, Peer Review process, Open access policy, Fast Publication, Full Archive for life time

Why Journal ICON

A Bi-Monthly and Multidisciplinary Journal, High Quality Papers, Peer Review process, Open access policy, Fast Publication, Full Archive for life time

Why Journal ICON

A Bi-Monthly and Multidisciplinary Journal, High Quality Papers, Peer Review process, Open access policy, Fast Publication, Full Archive for life time

Why Journal ICON

A Bi-Monthly and Multidisciplinary Journal, High Quality Papers, Peer Review process, Open access policy, Fast Publication, Full Archive for life time

Tuesday, November 20, 2018

Fault Tolerant FIFO Design For NOC Router Using Low Complextiy Voter

Journal ICON
Year: 2018 | Volume: 3 | Issue: 6 | Paper ID: ICON030618005
Fault Tolerant FIFO Design For NOC Router Using Low Complextiy Voter

R.Meena and D.L.Jayanthi

Abstract: The emerging technique for communication with in a large VLSI system is a Network On Chip. The fast scaling of technique there has been susceptible faults in the component of the Network On Chip, thus there is a requirement for technique to maintain circuit reliability. A fault-tolerant NOC (Network-on-chip) should be having the capacity to detect a fault and recover the system to correctly operate and work according to the mapped application. Deflection routing is a promising approach for energy and hardware efficient NOCs. The inherent redundancy of NOCs can be used to tolerate such failures. Redundancy techniques in NOC are implemented widely to increase the reliability, especially the TMR - Triple Modular Redundancy. This project proposes a simple but effective fault tolerant voter circuit for NOC which is more reliable and less expensive. Experimental results demonstrate its improvement over the former TMR structures. Proposed system has been coded in Verilog HDL and simulated using Xilinx 12.1.

VLSI Implementation Of Dead Pixel Removal Using Three Cell Sorting Median Filter

Journal ICON
Year: 2018 | Volume: 3 | Issue: 6 | Paper ID: ICON030618004
Multiple Cell Upset Tolerant Error Detection And Correction Code For  Semiconductor Memories Using DSSC

K.J.Lokesh and Prof. A.Vivekraj

Abstract: Median filtering (MF) is one such non-linear manipulation technique which is quite often used in number of applications such as to hide impulse noises. an SRAM-based FPGA implementation of this filter is then susceptible to configuration memory bit flips induced by single event upsets (SEU)sThe median finding algorithm often requires a basic two cell sorter which finds the higher pixel intensity and lower pixel intensity of two pixels. The proposed algorithm extensively operates on three pixels at a time either in row, column or right diagonal. In this paper, a fault-tolerant implementation of the median filter is presented and studied in¬depth. Our protection technique checks if the median output is within a dynamic range created with the remaining non-median outputs.So a three pixel sorting is the basic operation for this algorithm Hence we introduce three cell sorter to facilitate sorting. The output of the three cell sorter is maximum, middle and minimum of three pixels which are used for sorting. Our protection technique checks if the median output is within a dynamic range created with the remaining non-median outputs. An output error signal is activated if a corrupted image pixel is detected, then, a partial or complete reconfiguration can be performed to remove the configuration memory error.

Design And Implementation Of Karatsuba Based Fir Filters For Signal Processing

Journal ICON
Year: 2018 | Volume: 3 | Issue: 6 | Paper ID: ICON030618003
Design And Implementation Of Karatsuba Based Fir Filters For Signal Processing

N.Arunkumar and Prof. G.Kanagaraj

Abstract: Recursive combination of an algorithm based on Karatsuba multiplication is exploited to design a generalized transpose and Finite Impulse Response (FIR) Filter. Mid-range Karatsuba multiplication and Carry Save adder based on Karatsuba multiplication reduce time complexity for higher order multiplication implemented up to n-bit. The Karatsuba formula is used to speed-up the multiplication of large numbers by splitting the operands in two parts of equal length.As a result, we design modified N-tap Transpose and Parallel Symmetric FIR Filter Structure using Karatsuba algorithm for the automated processing of signal data. The mathematical formulation of the FFA Filter is derived. The proposed architecture involves significantly less area delay product (APD) then the existing block implementation.  The proposed structure achieves more than a half of the power reduction by adopting with and without proposed techniques compared to the earlier design structure. our proposed architecture has been coded HDL and simulated using Xilinx 12.1.

QCA Design Of Encoder For Low Power Memory Applications

Journal ICON
Year: 2018 | Volume: 3 | Issue: 6 | Paper ID: ICON030618002
QCA Design Of Encoder For Low Power Memory Applications

R.Bharathi Vidhya and Prof. G.Kanagaraj

Abstract: Quantum-dot fabrication and characterization is a well-established technology, which is used in photonics, quantum optics and nan electronics. Four quantum-dots placed at the corners of a square form a unit cell, which can hold a bit of information and serve as a basis for Quantum-dot Cellular Automata (QCA) nan electronic circuits. Although several basic QCA circuits have been designed, fabricated and tested, proving that quantum-dots can form functional, fast and low-power nan electronic circuits, QCA nan electronics still remain at its infancy. One of the reasons for this is the lack of design automation tools, which will facilitate the systematic design of large QCA circuits that contemporary applications demand. Here we present novel, programmable QCA circuits, which are based on crossbar architecture. These circuits can be programmed to implement any Boolean function in analogy to CMOS FPGAs and open the road that will lead to full design automation of QCA Nano electronic circuits. Using this architecture design and simulation of QCA circuits have proved to be area efficient, stable and reliable.

Multiple Cell Upset Tolerant Error Detection And Correction Code For Semiconductor Memories Using DSSC

Journal ICON
Year: 2018 | Volume: 3 | Issue: 6 | Paper ID: ICON030618001
Multiple Cell Upset Tolerant Error Detection And Correction Code For  Semiconductor Memories Using DSSC

V.Kalaivani and Prof.M.Rojaramani

Abstract: Errors that affect memories are a major issue in advanced electronic circuits. As technology scales, multiple bit errors become more likely. This limits the applicability of traditional protection techniques like Matrix code or single error correction codes that can correct only one error. Multiple errors tend to affect adjacent bits, and therefore it is interesting to use error correction codes that can correct adjacent errors. The issue with these codes is that they require a large area and delay that limits their use to protect flip-flops in circuits. This project presents the implementation and evaluation of the Data Segmentation Section Code (DSSC), a new algorithm for the detection and correction of multiple transient faults in volatile memories with low cost implementation. .our proposed system has been coded in Verilog HDL and simulated using Xilinx 12.1.