Tuesday, November 20, 2018

Fault Tolerant FIFO Design For NOC Router Using Low Complextiy Voter

Journal ICON
Year: 2018 | Volume: 3 | Issue: 6 | Paper ID: ICON030618005
Fault Tolerant FIFO Design For NOC Router Using Low Complextiy Voter

R.Meena and D.L.Jayanthi

Abstract: The emerging technique for communication with in a large VLSI system is a Network On Chip. The fast scaling of technique there has been susceptible faults in the component of the Network On Chip, thus there is a requirement for technique to maintain circuit reliability. A fault-tolerant NOC (Network-on-chip) should be having the capacity to detect a fault and recover the system to correctly operate and work according to the mapped application. Deflection routing is a promising approach for energy and hardware efficient NOCs. The inherent redundancy of NOCs can be used to tolerate such failures. Redundancy techniques in NOC are implemented widely to increase the reliability, especially the TMR - Triple Modular Redundancy. This project proposes a simple but effective fault tolerant voter circuit for NOC which is more reliable and less expensive. Experimental results demonstrate its improvement over the former TMR structures. Proposed system has been coded in Verilog HDL and simulated using Xilinx 12.1.