Tuesday, November 20, 2018

Multiple Cell Upset Tolerant Error Detection And Correction Code For Semiconductor Memories Using DSSC

Journal ICON
Year: 2018 | Volume: 3 | Issue: 6 | Paper ID: ICON030618001
Multiple Cell Upset Tolerant Error Detection And Correction Code For  Semiconductor Memories Using DSSC

V.Kalaivani and Prof.M.Rojaramani

Abstract: Errors that affect memories are a major issue in advanced electronic circuits. As technology scales, multiple bit errors become more likely. This limits the applicability of traditional protection techniques like Matrix code or single error correction codes that can correct only one error. Multiple errors tend to affect adjacent bits, and therefore it is interesting to use error correction codes that can correct adjacent errors. The issue with these codes is that they require a large area and delay that limits their use to protect flip-flops in circuits. This project presents the implementation and evaluation of the Data Segmentation Section Code (DSSC), a new algorithm for the detection and correction of multiple transient faults in volatile memories with low cost implementation. .our proposed system has been coded in Verilog HDL and simulated using Xilinx 12.1.