Tuesday, November 20, 2018

VLSI Implementation Of Dead Pixel Removal Using Three Cell Sorting Median Filter

Journal ICON
Year: 2018 | Volume: 3 | Issue: 6 | Paper ID: ICON030618004
Multiple Cell Upset Tolerant Error Detection And Correction Code For  Semiconductor Memories Using DSSC

K.J.Lokesh and Prof. A.Vivekraj

Abstract: Median filtering (MF) is one such non-linear manipulation technique which is quite often used in number of applications such as to hide impulse noises. an SRAM-based FPGA implementation of this filter is then susceptible to configuration memory bit flips induced by single event upsets (SEU)sThe median finding algorithm often requires a basic two cell sorter which finds the higher pixel intensity and lower pixel intensity of two pixels. The proposed algorithm extensively operates on three pixels at a time either in row, column or right diagonal. In this paper, a fault-tolerant implementation of the median filter is presented and studied in¬depth. Our protection technique checks if the median output is within a dynamic range created with the remaining non-median outputs.So a three pixel sorting is the basic operation for this algorithm Hence we introduce three cell sorter to facilitate sorting. The output of the three cell sorter is maximum, middle and minimum of three pixels which are used for sorting. Our protection technique checks if the median output is within a dynamic range created with the remaining non-median outputs. An output error signal is activated if a corrupted image pixel is detected, then, a partial or complete reconfiguration can be performed to remove the configuration memory error.